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ERC group
MSCA Group
Scientific Supervisor
Alberto A. Del Barrio
Contact email
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Research group
ArTeCS
Department
Computer Architecture and Automation
Faculty / Institute
Faculty of Computer Science and Engineering
Group description
The research activity of the Group of Architecture and Technology of Computing Systems (ArTeCS) of the Complutense University of Madrid (UCM) is focused on the conception and construction of digital information processing systems, and its efficient application regarding performance, energy consumption, and cost. Within this broad area, the group pays special attention to high-performance computing, processor & memory hierarchy design and embedded systems.
The research activity of the ArTeCS group covers a wide range of subjects related with high performance computing, computer architecture and system design. Furthermore, the ArTeCS group is one of the groups in UCM graded as “Excellent” by an evaluation commissioned by the State Research Agency.
Two of the most relevant researching lines of the group is the use of Specialized Arithmetic and Hardware Acceleration, both critical for performing the proposed project. Furthermore, ArTeCS belongs to the RISC-V National Excellence Network and represents UCM at RISC-V Foundation.
In relation to the project, recently we have released Deep PeNSieve, that is our framework to entirely train DNNs with posits on top of x86-64 architectures.
https://github.com/RaulMurillo/deep-pensieve
Research group website
Research topic
Nowadays, many applications are based on Deep Neural Networks (DNNs): autonomous vehicles, face detection, and even covid-19 detectors. Hence, improving the performance of DNNs is critical to scale such applications in the era of IoT and Big Data. Typically DNNs training has been done in 32-bit floating point, while the inference phase has been performed with reduced width integers. Version 3 universal numbers, aka posits, are a new format for representing real numbers introduced by John L. Gustafson in 2017 to mitigate the problems inherent in floating point, defined by the IEEE-754 standard. This format promises to achieve dynamic ranges similar to the floating point, reducing the bitwidth by half, so its impact on consumption, memory latency, operations execution time and more on any hardware system can be enormous. However, due to the novelty of the posits, they are not standard nor is there a system that runs them natively. This means that they have to be emulated through software libraries, which implies a huge loss of performance as soon as the application has a certain complexity. In the specific case of DNNs, the few studies tackling training with posits have achieved positive results on small feedforward-type networks. However, scaling training to DNNs like AlexNet, VGG or ResNet is a great challenge for the scientific community. The present project aims to develop a hardware accelerator based on RISC-V cores integrating the native support for posits, as well as the associated compilation software support, in order to efficiently perform the training of DNNs. Both the hardware and software developed will be publicly licensed for the benefit of the scientific community.
Research area
Information Science and Engineering (ENG), Mathematics (MAT), Physics (PHY)
Candidatures: requirements
A motivation letter identifying research synergies (max 1 page)
Your CV (including a list of publications) limited to a maximum of 4 pages
Short summary of your proposed project idea (max 1 page)
Candidatures: deadline
2021-07-15
Address
C/ Profesor José García Santesmases, 9; Ciudad Universitaria; 28040 - MADRID
Complutense University of Madrid
European Office
HRS4R
MSCA